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cpu/decoder - Simplify decoding by referencing registers by index

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madmaurice 2023-08-29 16:53:20 +02:00
parent eabc39590e
commit 310fb99ad2
3 changed files with 45 additions and 75 deletions
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27
cpu/cpu.cpp
View file

@ -19,6 +19,33 @@ u16 Cpu_state::getAF()
(carry ? 0x10 : 0);
}
u8& Cpu_state::reg8(u8 idx)
{
switch(idx)
{
case 0x0: return B; break;
case 0x1: return C; break;
case 0x2: return D; break;
case 0x3: return E; break;
case 0x4: return H; break;
case 0x5: return L; break;
case 0x7: return A; break;
default: panic("Invalid 8-bit register access idx=%d\n", idx);
}
}
u16& Cpu_state::reg16(u8 idx)
{
switch(idx)
{
case 0x0: return BC; break;
case 0x1: return DE; break;
case 0x2: return HL; break;
case 0x3: return SP; break;
default: panic("Invalid 16-bit register access idx=%d\n", idx);
}
}
Cpu::Cpu(Mem_device* bus)
: bus(bus)
{

3
cpu/cpu.h
View file

@ -93,6 +93,9 @@ struct Cpu_state {
void setAF(u16 v);
u16 getAF();
u8& reg8(u8 idx);
u16& reg16(u8 idx);
};
class Cpu {

90
cpu/decoder.cpp
View file

@ -22,26 +22,14 @@ void Cpu::executeInstruction()
u8 tmp;
switch(op & 0x07)
{
case 0x0: tmp = state.B; break;
case 0x1: tmp = state.C; break;
case 0x2: tmp = state.D; break;
case 0x3: tmp = state.E; break;
case 0x4: tmp = state.H; break;
case 0x5: tmp = state.L; break;
case 0x6: tmp = bus->read8(state.HL); break;
case 0x7: tmp = state.A; break;
default: tmp = state.reg8(op & 0x07); break;
};
switch((op >> 3) & 0x7)
{
case 0x0: state.B = tmp; break;
case 0x1: state.C = tmp; break;
case 0x2: state.D = tmp; break;
case 0x3: state.E = tmp; break;
case 0x4: state.H = tmp; break;
case 0x5: state.L = tmp; break;
case 0x6: bus->write8(state.HL, tmp); break;
case 0x7: state.A = tmp; break;
default: state.reg8((op >> 3) & 0x7) = tmp; break;
}
}
else if((op & 0xC7) == 0x06) // LD r, n
@ -50,59 +38,24 @@ void Cpu::executeInstruction()
switch((op >> 3) & 0x7)
{
case 0x0: state.B = imm; break;
case 0x1: state.C = imm; break;
case 0x2: state.D = imm; break;
case 0x3: state.E = imm; break;
case 0x4: state.H = imm; break;
case 0x5: state.L = imm; break;
case 0x6: bus->write8(state.HL, imm); break;
case 0x7: state.A = imm; break;
default: state.reg8((op >> 3) & 0x7) = imm; break;
}
}
else if((op & 0xC7) == 0x46 && op != 0x76) // LD r, [HL]
{
u8 data = bus->read8(state.HL);
switch((op >> 3) & 0x7)
{
case 0x0: state.B = data; break;
case 0x1: state.C = data; break;
case 0x2: state.D = data; break;
case 0x3: state.E = data; break;
case 0x4: state.H = data; break;
case 0x5: state.L = data; break;
case 0x7: state.A = data; break;
}
state.reg8((op >> 3) & 0x7) = data;
}
else if((op & 0xC8) == 0x70 && op != 0x76) // LD [HL], r
{
u8 data;
switch(op & 0x7)
{
case 0x0: data = state.B; break;
case 0x1: data = state.C; break;
case 0x2: data = state.D; break;
case 0x3: data = state.E; break;
case 0x4: data = state.H; break;
case 0x5: data = state.L; break;
case 0x7: data = state.A; break;
}
u8 data = state.reg8(op & 0x7);
bus->write8(state.HL, data);
}
else if((op & 0xCF) == 0x01) // LD rr, nn
{
u16 data = readPC16();
switch((op >> 4) & 0x3)
{
case 0x0: state.BC = data; break;
case 0x1: state.DE = data; break;
case 0x2: state.HL = data; break;
case 0x3: state.SP = data; break;
}
state.reg16((op >> 4) & 0x3) = data;
mcycles = 3;
}
else if((op & 0xCF) == 0xC5) // PUSH rr
@ -110,10 +63,8 @@ void Cpu::executeInstruction()
u16 data;
switch((op >> 4) & 0x3)
{
case 0x0: data = state.BC; break;
case 0x1: data = state.DE; break;
case 0x2: data = state.HL; break;
case 0x3: data = state.getAF(); break;
default: data = state.reg16((op >> 4) & 0x3);
}
state.SP-=2;
@ -130,10 +81,8 @@ void Cpu::executeInstruction()
switch((op >> 4) & 0x3)
{
case 0x0: state.BC = data; break;
case 0x1: state.DE = data; break;
case 0x2: state.HL = data; break;
case 0x3: state.setAF(data); break;
default: state.reg16((op >> 4) & 0x3) = data; break;
}
mcycles = 4;
@ -148,14 +97,8 @@ void Cpu::executeInstruction()
u8 rhs;
switch(op & 0x7)
{
case 0x0: rhs = state.B; break;
case 0x1: rhs = state.C; break;
case 0x2: rhs = state.D; break;
case 0x3: rhs = state.E; break;
case 0x4: rhs = state.H; break;
case 0x5: rhs = state.L; break;
case 0x6: rhs = bus->read8(state.HL); mcycles = 2; break;
case 0x7: rhs = state.A; break;
default: rhs = state.reg8(op & 0x7); break;
}
aluop8(aluop, rhs);
@ -166,14 +109,6 @@ void Cpu::executeInstruction()
switch((op >> 3) & 0x7)
{
case 0x0: aluop8(aluop, state.B, 1, state.B, false); break;
case 0x1: aluop8(aluop, state.C, 1, state.C, false); break;
case 0x2: aluop8(aluop, state.D, 1, state.D, false); break;
case 0x3: aluop8(aluop, state.E, 1, state.E, false); break;
case 0x4: aluop8(aluop, state.H, 1, state.C, false); break;
case 0x5: aluop8(aluop, state.L, 1, state.L, false); break;
case 0x7: aluop8(aluop, state.A, 1, state.A, false); break;
case 0x6:
{
u8 tmp = bus->read8(state.HL);
@ -182,8 +117,13 @@ void Cpu::executeInstruction()
mcycles = 3;
}
break;
default:
{
u8& reg = state.reg8((op >> 3) & 0x7);
aluop8(aluop, reg, 1, reg, false); break;
}
break;
}
}
else if((op & 0xE7) == 0xC2) // JP cc, nn:
{