From 39e041f473448d84397421352d2522324bd80d0f Mon Sep 17 00:00:00 2001
From: MadMaurice <madmaurice@zom.bi>
Date: Tue, 29 Aug 2023 21:25:19 +0200
Subject: [PATCH] cpu/decoder - Implement RLCA, RLA, RRCA, RRA

---
 cpu/decoder.cpp | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/cpu/decoder.cpp b/cpu/decoder.cpp
index 06b1116..9dfd0e8 100644
--- a/cpu/decoder.cpp
+++ b/cpu/decoder.cpp
@@ -298,6 +298,40 @@ void Cpu::executeInstruction()
           bus->write8(state.DE, state.A);
           mcycles = 2;
           break;
+        case 0x07: // RLCA
+          {
+            state.carry = (state.A & 0x80);
+            state.A = (state.A << 1) | (state.carry ? 0x01 : 0x00);
+            state.halfcarry = false;
+            state.subtract = false;
+            state.zero = false;
+          }
+        case 0x17: // RLA
+          {
+            bool msb_set = (state.A & 0x80);
+            state.A = (state.A << 1) | (state.carry ? 0x01 : 0x00);
+            state.carry = msb_set;
+            state.halfcarry = false;
+            state.subtract = false;
+            state.zero = false;
+          }
+        case 0x0F: // RRCA
+          {
+            state.carry = (state.A & 0x01);
+            state.A = (state.A >> 1) | (state.carry ? 0x80 : 0x00);
+            state.halfcarry = false;
+            state.subtract = false;
+            state.zero = false;
+          }
+        case 0x1F: // RRA
+          {
+            bool lsb_set = (state.A & 0x01);
+            state.A = (state.A >> 1) | (state.carry ? 0x80 : 0x00);
+            state.carry = lsb_set;
+            state.halfcarry = false;
+            state.subtract = false;
+            state.zero = false;
+          }
         case 0xFA: // LD A, [nn]
           state.A = bus->read8(readPC16());
           mcycles = 4;