cpu/decoder - Implement ADD HL, rr

This commit is contained in:
madmaurice 2023-08-29 23:05:22 +02:00
parent 8f1b1eb924
commit 41c4038d0a
2 changed files with 12 additions and 0 deletions

View file

@ -172,6 +172,16 @@ void Cpu::executeInstruction()
mcycles = 3;
}
}
else if((op & 0xCF) == 0x09) // ADD HL, rr
{
u16 rhs = state.reg16((op >> 4) & 0x3);
u16 res12 = (state.HL & 0x0FFF) + (rhs & 0x0FFF);
state.halfcarry = (res11 & 0x1000);
u32 res32 = (u32)state.HL + (u32)rhs;
state.carry = (res32 & 0x10000);
state.subtract = false;
mcycles = 2;
}
else if((op & 0xE7) == 0xC0) // RET cc
{
if(decodeCond((op >> 3) & 0x3))

View file

@ -2,6 +2,8 @@
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned int u32;
typedef signed char s8;
typedef signed short s16;
typedef signed int s32;