From 8d063c08cae2fa73b88504c4b51777070bcfc351 Mon Sep 17 00:00:00 2001 From: MadMaurice Date: Sat, 26 Aug 2023 21:17:47 +0200 Subject: [PATCH] Fix build errors. --- Makeconf | 5 +- cpu/cpu.h | 14 ++--- cpu/decoder.cpp | 142 ++++++++++++++++++++++++++++++++---------------- memory/ram.cpp | 4 +- 4 files changed, 106 insertions(+), 59 deletions(-) diff --git a/Makeconf b/Makeconf index 0e0571e..edb02e6 100644 --- a/Makeconf +++ b/Makeconf @@ -1,5 +1,6 @@ modules := test \ - memory/bus \ - memory/ram + memory/bus \ + memory/ram \ + cpu/decoder CXX_FLAGS := -I $(CURDIR) diff --git a/cpu/cpu.h b/cpu/cpu.h index 81858cc..c4a91fd 100644 --- a/cpu/cpu.h +++ b/cpu/cpu.h @@ -12,11 +12,6 @@ enum Flags { F_CARRY = 0x1, }; -union Register_pair { - struct { u8 hi; u8 lo; } - u16 hilo; -}; - struct Cpu_state { // Registers union { @@ -50,11 +45,14 @@ private: typedef u8 opcode_t; private: - u8 readPC(); + u8 readPC8(); + u16 readPC16(); - void pushStack(u8 data); - u8 popStack(); + void pushStack8(u8 data); + u8 popStack8(); + void pushStack16(u16 data); + u16 popStack16(); public: Cpu(); diff --git a/cpu/decoder.cpp b/cpu/decoder.cpp index 0161dbd..b2f0492 100644 --- a/cpu/decoder.cpp +++ b/cpu/decoder.cpp @@ -1,4 +1,5 @@ #include "cpu/cpu.h" +#include "memory/mem_device.h" u8 Cpu::readPC8() { @@ -14,26 +15,26 @@ u16 Cpu::readPC16() return data; } -void pushStack8(u8 data) +void Cpu::pushStack8(u8 data) { bus->write8(state.SP, data); state.SP--; } -u8 popStack8() +u8 Cpu::popStack8() { u8 data = bus->read8(state.SP); state.SP++; return data; } -void pushStack16(u16 data) +void Cpu::pushStack16(u16 data) { bus->write16(state.SP,data); state.SP-=2; } -void popStack16() +u16 Cpu::popStack16() { u16 data = bus->read16(state.SP); state.SP+=2; @@ -42,67 +43,114 @@ void popStack16() void Cpu::step() { - opcode_t op = readPC(); + opcode_t op = readPC8(); int mcycles = 1; + switch(op) { - 0x00: // NOP - (void) ;; + case 0x00: break; // NOP - 0x01: // LD BC, n16 - state.BC = readPC16(); mcycles = 12;; - 0x11: // LD DE, n16 - state.DE = readPC16(); mcycles = 12;; - 0x21: // LD HL, n16 - state.HL = readPC16(); mcycles = 12;; - 0x31: // LD SP, n16 - state.SP = readPC16(); mcycles = 12;; + case 0x01: // LD BC, n16 + state.BC = readPC16(); mcycles = 12; break; + case 0x11: // LD DE, n16 + state.DE = readPC16(); mcycles = 12; break; + case 0x21: // LD HL, n16 + state.HL = readPC16(); mcycles = 12; break; + case 0x31: // LD SP, n16 + state.SP = readPC16(); mcycles = 12; break; - 0x02: // LD [BC], A - bus->write8(state.BC, state.A); mcycles = 8;; - 0x12: // LD [DE], A - bus->write8(state.DE, state.A); mcycles = 8;; - 0x22: // LD [HL+], A - bus->write8(state.HL, state.A); state.HL++; mcycles = 8;; - 0x32: // LD [HL-], A - bus->write8(state.HL, state.A); state.HL--; mcycles = 8;; + case 0x02: // LD [BC], A + bus->write8(state.BC, state.A); mcycles = 8; break; + case 0x12: // LD [DE], A + bus->write8(state.DE, state.A); mcycles = 8; break; + case 0x22: // LD [HL+], A + bus->write8(state.HL, state.A); state.HL++; mcycles = 8; break; + case 0x32: // LD [HL-], A + bus->write8(state.HL, state.A); state.HL--; mcycles = 8; break; - 0x03: // INC BC - state.BC++; mcycles = 2;; - 0x13: // INC DE - state.DE++; mcycles = 2;; - 0x23: // INC HL - state.HL++; mcycles = 2;; - 0x33: // INC SP - state.SP++; mcycles = 2;; + case 0x03: // INC BC + state.BC++; mcycles = 2; break; + case 0x13: // INC DE + state.DE++; mcycles = 2; break; + case 0x23: // INC HL + state.HL++; mcycles = 2; break; + case 0x33: // INC SP + state.SP++; mcycles = 2; break; - 0x04: // INC B + case 0x04: // INC B state.B++; state.zero = (state.B == 0); state.subtract = false; state.halfcarry = (state.B & 0x0F == 0); - ; - 0x14: // INC D + break; + case 0x14: // INC D state.D++; state.zero = (state.D == 0); state.subtract = false; state.halfcarry = (state.D & 0x0F == 0); - ; - 0x24: // INC H + break; + case 0x24: // INC H state.H++; state.zero = (state.H == 0); state.subtract = false; state.halfcarry = (state.H & 0x0F == 0); - ; - 0x34: // INC [HL] - u8 data = bus->read8(state.HL); - data++; - bus->write8(state.HL, data); - state.zero = (data == 0); - state.subtract = false; - state.halfcarry = (data & 0x0F == 0); + break; + case 0x34: // INC [HL] + { + u8 data = bus->read8(state.HL); + data++; + bus->write8(state.HL, data); + state.zero = (data == 0); + state.subtract = false; + state.halfcarry = (data & 0x0F == 0); + mcycles = 3; + } + break; + + case 0x05: // INC B + state.B--; + state.zero = (state.B == 0); + state.subtract = true; + state.halfcarry = (state.B & 0x0F == 0x0F); + break; + case 0x15: // INC D + state.D--; + state.zero = (state.D == 0); + state.subtract = true; + state.halfcarry = (state.D & 0x0F == 0x0F); + break; + case 0x25: // INC H + state.H--; + state.zero = (state.H == 0); + state.subtract = true; + state.halfcarry = (state.H & 0x0F == 0x0F); + break; + case 0x35: // INC [HL] + { + u8 data = bus->read8(state.HL); + data--; + bus->write8(state.HL, data); + state.zero = (data == 0); + state.subtract = true; + state.halfcarry = (data & 0x0F == 0x0F); + mcycles = 3; + } + break; + + case 0x06: // LD B, n8 + state.B = readPC8(); + mcycles = 2; + break; + case 0x16: // LD D, n8 + state.D = readPC8(); + mcycles = 2; + break; + case 0x26: // LD H, n8 + state.H = readPC8(); + mcycles = 2; + break; + case 0x36: // LD [HL], n8 + bus->write8(state.HL, readPC8()); mcycles = 3; - ; - - + break; } } diff --git a/memory/ram.cpp b/memory/ram.cpp index 3c445a5..d84ea6e 100644 --- a/memory/ram.cpp +++ b/memory/ram.cpp @@ -4,7 +4,7 @@ RAM::RAM(u16 size) : size(size), readonly(false) { memory = new u8[size]; } -RAM::RAM(u8* memory, u16 size, bool readonly = false) +RAM::RAM(u8* memory, u16 size, bool readonly) : memory(memory), size(size), readonly(readonly) {} @@ -25,7 +25,7 @@ void RAM::write16(u16 addr, u16 data) { } u16 RAM::read16(u16 addr) { - if(addr >= size - 1) return; + if(addr >= size - 1) return 0xFFFFu; u16 *ptr = (u16*)&memory[addr]; return *ptr; }