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Simplify decoder code somewhat.

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madmaurice 2023-08-27 00:15:12 +02:00
parent ab09bbd9b7
commit 93521e559c
1 changed files with 55 additions and 12 deletions
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67
cpu/decoder.cpp
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@ -46,9 +46,9 @@ void Cpu::step()
opcode_t op = readPC8(); opcode_t op = readPC8();
int mcycles = 1; int mcycles = 1;
if ((op & 0xC0 == 0x40) && op != 0x76) // Lots of LD (0x76 is HALT) if ((op & 0xC0 == 0x40) && op != 0x76) // LD r, r'
{ {
u9 tmp; u8 tmp;
switch(op & 0x07) switch(op & 0x07)
{ {
case 0x0: tmp = state.B; break; case 0x0: tmp = state.B; break;
@ -61,21 +61,64 @@ void Cpu::step()
case 0x7: tmp = state.A; break; case 0x7: tmp = state.A; break;
}; };
switch(op & 0x38) switch((op >> 3) & 0x7)
{ {
case 0x00: state.B = tmp; break; case 0x0: state.B = tmp; break;
case 0x10: state.D = tmp; break; case 0x1: state.C = tmp; break;
case 0x20: state.H = tmp; break; case 0x2: state.D = tmp; break;
case 0x30: bus->write8(state.HL, tmp); break; case 0x3: state.E = tmp; break;
case 0x08: state.C = tmp; break; case 0x4: state.H = tmp; break;
case 0x18: state.E = tmp; break; case 0x5: state.L = tmp; break;
case 0x28: state.L = tmp; break; case 0x6: bus->write8(state.HL, tmp); break;
case 0x38: state.A = tmp; break; case 0x7: state.A = tmp; break;
} }
} }
else if(op & 0xC7 == 0x06) else if(op & 0xC7 == 0x06) // LD r, n
{ {
u8 imm = readPC8();
switch((op >> 3) & 0x7)
{
case 0x0: state.B = imm; break;
case 0x1: state.C = imm; break;
case 0x2: state.D = imm; break;
case 0x3: state.E = imm; break;
case 0x4: state.H = imm; break;
case 0x5: state.L = imm; break;
case 0x6: bus->write8(state.HL, tmp); break;
case 0x7: state.A = imm; break;
}
}
else if(op & 0xC7 == 0x46 && op != 0x76) // LD r, [HL]
{
u8 data = bus->read8(state.HL);
switch((op >> 3) & 0x7)
{
case 0x0: state.B = imm; break;
case 0x1: state.C = imm; break;
case 0x2: state.D = imm; break;
case 0x3: state.E = imm; break;
case 0x4: state.H = imm; break;
case 0x5: state.L = imm; break;
case 0x7: state.A = imm; break;
}
}
else if(op & 0xC8 == 0x70 && op != 0x76) // LD [HL], r
{
u8 data;
switch(op & 0x7)
{
case 0x0: data = state.B; break;
case 0x1: data = state.C; break;
case 0x2: data = state.D; break;
case 0x3: data = state.E; break;
case 0x4: data = state.H; break;
case 0x5: data = state.L; break;
case 0x7: data = state.A; break;
}
bus->write8(state.HL, data);
} }
else else
{ {