more decoder code
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8d063c08ca
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1 changed files with 295 additions and 103 deletions
398
cpu/decoder.cpp
398
cpu/decoder.cpp
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@ -46,111 +46,303 @@ void Cpu::step()
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opcode_t op = readPC8();
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int mcycles = 1;
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switch(op) {
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case 0x00: break; // NOP
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case 0x01: // LD BC, n16
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state.BC = readPC16(); mcycles = 12; break;
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case 0x11: // LD DE, n16
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state.DE = readPC16(); mcycles = 12; break;
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case 0x21: // LD HL, n16
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state.HL = readPC16(); mcycles = 12; break;
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case 0x31: // LD SP, n16
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state.SP = readPC16(); mcycles = 12; break;
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case 0x02: // LD [BC], A
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bus->write8(state.BC, state.A); mcycles = 8; break;
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case 0x12: // LD [DE], A
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bus->write8(state.DE, state.A); mcycles = 8; break;
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case 0x22: // LD [HL+], A
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bus->write8(state.HL, state.A); state.HL++; mcycles = 8; break;
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case 0x32: // LD [HL-], A
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bus->write8(state.HL, state.A); state.HL--; mcycles = 8; break;
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case 0x03: // INC BC
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state.BC++; mcycles = 2; break;
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case 0x13: // INC DE
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state.DE++; mcycles = 2; break;
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case 0x23: // INC HL
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state.HL++; mcycles = 2; break;
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case 0x33: // INC SP
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state.SP++; mcycles = 2; break;
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case 0x04: // INC B
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state.B++;
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state.zero = (state.B == 0);
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state.subtract = false;
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state.halfcarry = (state.B & 0x0F == 0);
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break;
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case 0x14: // INC D
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state.D++;
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state.zero = (state.D == 0);
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state.subtract = false;
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state.halfcarry = (state.D & 0x0F == 0);
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break;
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case 0x24: // INC H
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state.H++;
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state.zero = (state.H == 0);
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state.subtract = false;
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state.halfcarry = (state.H & 0x0F == 0);
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break;
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case 0x34: // INC [HL]
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if ((op & 0xC0 == 0x40) && op != 0x76) // Lots of LD (0x76 is HALT)
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{
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u8 data = bus->read8(state.HL);
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data++;
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bus->write8(state.HL, data);
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state.zero = (data == 0);
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state.subtract = false;
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state.halfcarry = (data & 0x0F == 0);
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mcycles = 3;
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}
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break;
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u9 tmp;
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switch(op & 0x07)
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{
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case 0x0: tmp = state.B; break;
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case 0x1: tmp = state.C; break;
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case 0x2: tmp = state.D; break;
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case 0x3: tmp = state.E; break;
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case 0x4: tmp = state.H; break;
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case 0x5: tmp = state.L; break;
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case 0x6: tmp = bus->read8(state.HL); break;
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case 0x7: tmp = state.A; break;
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};
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case 0x05: // INC B
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state.B--;
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state.zero = (state.B == 0);
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state.subtract = true;
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state.halfcarry = (state.B & 0x0F == 0x0F);
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break;
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case 0x15: // INC D
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state.D--;
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state.zero = (state.D == 0);
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state.subtract = true;
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state.halfcarry = (state.D & 0x0F == 0x0F);
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break;
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case 0x25: // INC H
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state.H--;
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state.zero = (state.H == 0);
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state.subtract = true;
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state.halfcarry = (state.H & 0x0F == 0x0F);
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break;
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case 0x35: // INC [HL]
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switch(op & 0x38)
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{
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case 0x00: state.B = tmp; break;
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case 0x10: state.D = tmp; break;
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case 0x20: state.H = tmp; break;
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case 0x30: bus->write8(state.HL, tmp); break;
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case 0x08: state.C = tmp; break;
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case 0x18: state.E = tmp; break;
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case 0x28: state.L = tmp; break;
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case 0x38: state.A = tmp; break;
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}
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}
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else if(op & 0xC7 == 0x06)
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{
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u8 data = bus->read8(state.HL);
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data--;
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bus->write8(state.HL, data);
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state.zero = (data == 0);
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state.subtract = true;
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state.halfcarry = (data & 0x0F == 0x0F);
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mcycles = 3;
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}
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break;
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case 0x06: // LD B, n8
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state.B = readPC8();
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mcycles = 2;
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break;
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case 0x16: // LD D, n8
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state.D = readPC8();
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mcycles = 2;
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break;
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case 0x26: // LD H, n8
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state.H = readPC8();
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mcycles = 2;
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break;
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case 0x36: // LD [HL], n8
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bus->write8(state.HL, readPC8());
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mcycles = 3;
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break;
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}
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}
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else
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{
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switch(op)
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{
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case 0x00: break; // NOP
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case 0x01: // LD BC, n16
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state.BC = readPC16(); mcycles = 12; break;
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case 0x11: // LD DE, n16
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state.DE = readPC16(); mcycles = 12; break;
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case 0x21: // LD HL, n16
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state.HL = readPC16(); mcycles = 12; break;
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case 0x31: // LD SP, n16
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state.SP = readPC16(); mcycles = 12; break;
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case 0x02: // LD [BC], A
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bus->write8(state.BC, state.A); mcycles = 8; break;
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case 0x12: // LD [DE], A
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bus->write8(state.DE, state.A); mcycles = 8; break;
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case 0x22: // LD [HL+], A
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bus->write8(state.HL, state.A); state.HL++; mcycles = 8; break;
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case 0x32: // LD [HL-], A
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bus->write8(state.HL, state.A); state.HL--; mcycles = 8; break;
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case 0x03: // INC BC
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state.BC++; mcycles = 2; break;
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case 0x13: // INC DE
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state.DE++; mcycles = 2; break;
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case 0x23: // INC HL
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state.HL++; mcycles = 2; break;
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case 0x33: // INC SP
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state.SP++; mcycles = 2; break;
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case 0x04: // INC B
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state.B++;
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state.zero = (state.B == 0);
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state.subtract = false;
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state.halfcarry = (state.B & 0x0F == 0);
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break;
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case 0x14: // INC D
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state.D++;
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state.zero = (state.D == 0);
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state.subtract = false;
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state.halfcarry = (state.D & 0x0F == 0);
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break;
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case 0x24: // INC H
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state.H++;
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state.zero = (state.H == 0);
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state.subtract = false;
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state.halfcarry = (state.H & 0x0F == 0);
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break;
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case 0x34: // INC [HL]
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{
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u8 data = bus->read8(state.HL);
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data++;
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bus->write8(state.HL, data);
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state.zero = (data == 0);
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state.subtract = false;
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state.halfcarry = (data & 0x0F == 0);
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mcycles = 3;
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}
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break;
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case 0x05: // INC B
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state.B--;
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state.zero = (state.B == 0);
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state.subtract = true;
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state.halfcarry = (state.B & 0x0F == 0x0F);
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break;
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case 0x15: // INC D
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state.D--;
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state.zero = (state.D == 0);
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state.subtract = true;
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state.halfcarry = (state.D & 0x0F == 0x0F);
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break;
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case 0x25: // INC H
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state.H--;
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state.zero = (state.H == 0);
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state.subtract = true;
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state.halfcarry = (state.H & 0x0F == 0x0F);
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break;
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case 0x35: // INC [HL]
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{
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u8 data = bus->read8(state.HL);
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data--;
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bus->write8(state.HL, data);
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state.zero = (data == 0);
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state.subtract = true;
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state.halfcarry = (data & 0x0F == 0x0F);
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mcycles = 3;
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}
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break;
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case 0x06: // LD B, n8
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state.B = readPC8();
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mcycles = 2;
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break;
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case 0x16: // LD D, n8
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state.D = readPC8();
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mcycles = 2;
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break;
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case 0x26: // LD H, n8
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state.H = readPC8();
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mcycles = 2;
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break;
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case 0x36: // LD [HL], n8
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bus->write8(state.HL, readPC8());
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mcycles = 3;
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break;
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case 0x07: // RLCA
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case 0x17: // RLA
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case 0x27: // DAA
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case 0x37: // SCF
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break;
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case 0x08: // LD [a16], SP
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{
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u16 addr = readPC16();
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bus->write16(addr, state.SP);
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mcycles = 5;
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}
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break;
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case 0x18: // JR e8
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{
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s8 rel = readPC8();
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state.PC = state.PC + rel;
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mcycles = 3;
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}
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break;
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case 0x28: // JR Z, e8
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{
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s8 rel = readPC8();
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if (state.zero)
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{
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state.PC = state.PC + rel;
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mcycles = 3;
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}
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else
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{
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mcycles = 2;
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}
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}
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break;
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case 0x38: // JR C, e8
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{
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s8 rel = readPC8();
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if (state.carry)
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{
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state.PC = state.PC + rel;
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mcycles = 3;
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}
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else
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{
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mcycles = 2;
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}
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}
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break;
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case 0x09: // ADD HL, BC
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case 0x19: // ADD HL, DE
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case 0x29: // ADD HL, HL
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case 0x39: // ADD HL, SP
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// TODO
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break;
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case 0x0A: // LD A, [BC]
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state.A = bus->read8(state.BC);
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break;
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case 0x1A: // LD A, [DE]
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state.A = bus->read8(state.DE);
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break;
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case 0x2A: // LD A, [HL+]
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state.A = bus->read8(state.HL);
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state.HL++;
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break;
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case 0x3A: // LD A, [HL-]
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state.A = bus->read8(state.HL);
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state.HL--;
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break;
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case 0x0B: // DEC BC
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state.BC--;
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break;
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case 0x1B: // DEC DE
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state.DE--;
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break;
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case 0x2B: // DEC HL
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state.HL--;
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break;
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case 0x3B: // DEC SP
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state.SP--;
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break;
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case 0x0C: // INC C
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state.C++;
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state.zero = (state.C == 0);
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state.subtract = false;
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state.halfcarry = (state.C & 0x0F == 0);
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break;
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case 0x1C: // INC E
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state.E++;
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state.zero = (state.E == 0);
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state.subtract = false;
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state.halfcarry = (state.E & 0x0F == 0);
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break;
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case 0x2C: // INC L
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state.L++;
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state.zero = (state.L == 0);
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state.subtract = false;
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state.halfcarry = (state.L & 0x0F == 0);
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break;
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case 0x3C: // INC A
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state.A++;
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state.zero = (state.A == 0);
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state.subtract = false;
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state.halfcarry = (state.A & 0x0F == 0);
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break;
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case 0x0D: // DEC C
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state.C--;
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state.zero = (state.C == 0);
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state.subtract = true;
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state.halfcarry = (state.C & 0x0F == 0x0F);
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break;
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case 0x1D: // DEC E
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state.E--;
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state.zero = (state.E == 0);
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state.subtract = true;
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state.halfcarry = (state.E & 0x0F == 0x0F);
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break;
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case 0x2D: // DEC L
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state.L--;
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state.zero = (state.L == 0);
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state.subtract = true;
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state.halfcarry = (state.L & 0x0F == 0x0F);
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break;
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case 0x3D: // DEC A
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state.A--;
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state.zero = (state.A == 0);
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state.subtract = true;
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state.halfcarry = (state.A & 0x0F == 0x0F);
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break;
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case 0x0E: // LD C, n8
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state.C = readPC8();
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mcycles = 2;
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break;
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case 0x1E: // LD E, n8
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state.E = readPC8();
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mcycles = 2;
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break;
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case 0x2E: // LD L, n8
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state.L = readPC8();
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mcycles = 2;
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break;
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case 0x3E: // LD A, n8
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state.A = readPC8();
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mcycles = 2;
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break;
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case 0x0F: // RRCA
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case 0x1F: // RRA
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case 0x2F: // CPL
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case 0x3F: // CCF
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// TODO
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break;
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}
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}
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}
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