2023-08-29 23:11:31 +02:00
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#include <cpu/cpu.h>
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2023-09-01 15:11:27 +02:00
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#include <iostream>
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#include <sstream>
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#include <cstring>
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#include <iomanip>
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2023-08-27 22:19:02 +02:00
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void Cpu_state::setAF(u16 v)
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{
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A = (u8)(v >> 8);
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zero = (v & 0x80 != 0);
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subtract = (v & 0x40 != 0);
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halfcarry = (v & 0x20 != 0);
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carry = (v & 0x10 != 0);
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}
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u16 Cpu_state::getAF()
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{
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return ((u16)A << 8) |
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(zero ? 0x80 : 0) |
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(subtract ? 0x40 : 0) |
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(halfcarry ? 0x20 : 0) |
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(carry ? 0x10 : 0);
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}
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2023-09-01 23:19:02 +02:00
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u8 Cpu_state::getF()
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{
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return (zero ? 0x80 : 0) |
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(subtract ? 0x40 : 0) |
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(halfcarry ? 0x20 : 0) |
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(carry ? 0x10 : 0);
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}
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2023-09-01 15:11:27 +02:00
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u8& Cpu_state::reg8(Cpu& cpu, u8 idx)
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2023-08-29 16:53:20 +02:00
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{
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switch(idx)
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{
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case 0x0: return B; break;
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case 0x1: return C; break;
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case 0x2: return D; break;
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case 0x3: return E; break;
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case 0x4: return H; break;
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case 0x5: return L; break;
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case 0x7: return A; break;
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2023-09-01 15:11:27 +02:00
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default: throw CpuException(cpu, "Invalid 8-bit register access");
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2023-08-29 16:53:20 +02:00
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}
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}
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2023-09-01 15:11:27 +02:00
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u16& Cpu_state::reg16(Cpu& cpu, u8 idx)
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2023-08-29 16:53:20 +02:00
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{
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switch(idx)
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{
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case 0x0: return BC; break;
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case 0x1: return DE; break;
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case 0x2: return HL; break;
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case 0x3: return SP; break;
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2023-09-01 15:11:27 +02:00
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default: throw CpuException(cpu, "Invalid 16-bit register access");
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2023-08-29 16:53:20 +02:00
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}
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}
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2023-08-28 21:56:33 +02:00
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Cpu::Cpu(Mem_device* bus)
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: bus(bus)
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{
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reset();
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}
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void Cpu::step()
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{
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2023-08-30 00:01:45 +02:00
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if(state.stopped) return;
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2023-08-29 23:46:36 +02:00
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2023-08-29 13:45:17 +02:00
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if(!handleInterrupts()) // if no isr has been called, decode an instruction
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{
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2023-08-30 00:01:45 +02:00
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if (state.halted)
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2023-08-29 23:30:31 +02:00
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processed_mcycles += 4;
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else
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executeInstruction();
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2023-08-29 13:45:17 +02:00
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}
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2023-08-28 21:56:33 +02:00
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}
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void Cpu::reset()
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{
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state.BC = 0;
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state.DE = 0;
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state.HL = 0;
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state.A = 0;
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state.SP = 0;
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state.PC = 0;
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state.zero = false;
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state.subtract = false;
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state.halfcarry = false;
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state.carry = false;
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state.IME = IME_OFF;
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state.IE = 0;
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state.IF = 0;
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2023-08-29 23:30:31 +02:00
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2023-08-30 00:01:45 +02:00
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state.halted = false;
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2023-08-30 21:47:38 +02:00
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state.haltbug = false;
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2023-08-30 00:01:45 +02:00
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state.stopped = false;
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2023-08-28 21:56:33 +02:00
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}
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u8 Cpu::readPC8()
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{
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u8 data = bus->read8(state.PC);
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2023-08-30 21:47:38 +02:00
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if(!state.haltbug)
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state.PC++;
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else
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state.haltbug = false;
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2023-08-28 21:56:33 +02:00
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return data;
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}
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u16 Cpu::readPC16()
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{
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2023-08-30 21:47:38 +02:00
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u16 data;
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if(state.haltbug)
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{
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data = bus->read8(state.PC);
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data |= data << 8; // Same byte twice
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state.PC++;
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state.haltbug = false;
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}
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else
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{
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data = bus->read16(state.PC);
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state.PC+=2;
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}
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2023-08-28 21:56:33 +02:00
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return data;
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}
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void Cpu::pushStack8(u8 data)
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{
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state.SP--;
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2023-08-29 12:10:10 +02:00
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bus->write8(state.SP, data);
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2023-08-28 21:56:33 +02:00
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}
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u8 Cpu::popStack8()
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{
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u8 data = bus->read8(state.SP);
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state.SP++;
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return data;
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}
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void Cpu::pushStack16(u16 data)
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{
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state.SP-=2;
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2023-08-29 12:10:10 +02:00
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bus->write16(state.SP,data);
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2023-08-28 21:56:33 +02:00
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}
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u16 Cpu::popStack16()
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{
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u16 data = bus->read16(state.SP);
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state.SP+=2;
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return data;
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}
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void Cpu::doCall(u16 target)
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{
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pushStack16(state.PC);
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state.PC = target;
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}
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void Cpu::doRet()
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{
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state.PC = popStack16();
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}
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2023-08-29 13:45:55 +02:00
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void Cpu::signalInterrupt(InterruptType it)
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{
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state.IF |= it;
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}
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2023-08-28 21:56:33 +02:00
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bool Cpu::decodeCond(u8 cc)
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{
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switch(cc)
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{
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case COND_NZ: return !state.zero; break;
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case COND_Z: return state.zero; break;
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case COND_NC: return !state.carry; break;
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case COND_C: return state.carry; break;
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}
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return false;
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}
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2023-08-27 22:19:02 +02:00
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void Cpu::aluop8(AluOp op, u8 lhs, u8 rhs, u8& out, bool update_carry)
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{
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u16 rhs16 = rhs;
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u16 res16;
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u8 res;
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if ((op == ADC || op == SBC) && state.carry)
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rhs16++;
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u16 lhs_lower = lhs & 0x0F;
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u16 lhs_upper = lhs & 0xF0;
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u16 rhs_lower = rhs16 & 0x0F;
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u16 rhs_upper = rhs16 & 0x1F0;
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switch(op)
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{
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case ADD:
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case ADC:
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res16 = lhs_lower + rhs_lower;
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break;
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case SUB:
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case SBC:
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case CP:
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res16 = lhs_lower - rhs_lower;
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break;
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case AND:
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res16 = lhs_lower & rhs_lower;
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break;
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case OR:
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res16 = lhs_lower | rhs_lower;
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break;
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case XOR:
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res16 = lhs_lower ^ rhs_lower;
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break;
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}
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state.halfcarry = (res16 & 0x10 != 0) || op == AND;
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state.subtract = (op == SUB) || (op == SBC) || (op == CP);
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switch(op)
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{
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case ADD:
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case ADC:
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res16 += lhs_upper + rhs_upper;
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break;
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case SUB:
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case SBC:
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case CP:
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res16 += lhs_upper - rhs_upper;
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break;
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case AND:
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res16 |= lhs_upper & rhs_upper;
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break;
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case OR:
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res16 |= lhs_upper | rhs_upper;
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break;
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case XOR:
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res16 |= lhs_upper ^ rhs_upper;
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break;
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}
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res = (u8)(res16 & 0xFF);
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if(update_carry)
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state.carry = (res16 & 0x100 != 0);
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state.zero = (res == 0);
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if (op != CP)
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out = res;
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}
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2023-08-28 21:56:33 +02:00
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2023-09-01 15:11:27 +02:00
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void Cpu::add16(u16& out, u16 lhs, u16 rhs)
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{
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u16 res11 = (lhs & 0x0FFF) + (rhs & 0x0FFF);
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state.halfcarry = (res11 & 0x1000);
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u32 res32 = lhs + rhs;
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state.carry = (res32 & 0x10000);
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state.subtract = false;
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lhs = (u16)res32;
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}
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2023-08-29 13:45:17 +02:00
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bool Cpu::handleInterrupts()
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2023-08-28 21:56:33 +02:00
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{
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2023-08-29 23:30:31 +02:00
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// Once there's an interrupt we exit halt mode
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2023-08-30 21:47:38 +02:00
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if (state.SI())
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2023-08-30 00:01:45 +02:00
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state.halted = false;
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2023-08-29 23:30:31 +02:00
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2023-08-28 21:56:33 +02:00
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if (state.IME == IME_SCHEDULED)
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state.IME = IME_ON;
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2023-08-30 22:13:58 +02:00
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else if (state.IME == IME_ON && state.SI() != 0)
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2023-08-28 21:56:33 +02:00
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{
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u16 isr;
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InterruptType it;
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2023-08-30 22:13:58 +02:00
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if (state.SI() & INT_VBlank) { it = INT_VBlank; isr = 0x40; }
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else if (state.SI() & INT_LCDSTAT) { it = INT_LCDSTAT; isr = 0x48; }
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else if (state.SI() & INT_Timer) { it = INT_Timer; isr = 0x50; }
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else if (state.SI() & INT_Serial) { it = INT_Serial; isr = 0x58; }
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else if (state.SI() & INT_Joypad) { it = INT_Joypad; isr = 0x60; }
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2023-09-01 15:11:27 +02:00
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else throw CpuException(*this, "Unable to find interrupt");
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2023-08-28 21:56:33 +02:00
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state.IME = IME_OFF; // Disable IME
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state.IF &= ~it; // clear interrupt in IF
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doCall(isr); // Call interrupt service routine
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processed_mcycles += 5;
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2023-08-29 13:45:17 +02:00
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return true;
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2023-08-28 21:56:33 +02:00
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}
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2023-08-29 13:45:17 +02:00
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return false;
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2023-08-28 21:56:33 +02:00
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}
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2023-09-01 15:11:27 +02:00
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CpuException::CpuException(Cpu& cpu, const char* msg)
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: EmulatorException(msg), state(cpu.state), instaddr(cpu.last_instr_addr)
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{
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for(u16 offset; offset < 4; offset++)
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instmem[offset] = cpu.bus->read8(cpu.last_instr_addr + offset);
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}
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const char* CpuException::what() const noexcept
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{
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std::stringstream s;
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#define FORMAT16(x) std::uppercase << std::hex << std::setfill('0') << std::setw(4) << x
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#define FORMAT8(x) std::uppercase << std::hex << std::setfill('0') << std::setw(2) << ((unsigned)(x))
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s << "CpuException: " << std::runtime_error::what() << std::endl
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<< "Last Instruction @" << FORMAT16(instaddr) << " : "
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<< FORMAT8(instmem[0]) << " "
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<< FORMAT8(instmem[1]) << " "
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<< FORMAT8(instmem[2]) << " "
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<< FORMAT8(instmem[3]) << std::endl
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<< "Registers:" << std::endl
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<< " A=" << FORMAT8(state.A) << " Z=" << state.zero << " N=" << state.subtract << " H=" << state.halfcarry << " C=" << state.carry
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<< " IME=" << state.IME << " IE=" << FORMAT8(state.IE) << " IF=" << FORMAT8(state.IF) << std::endl
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<< " BC=" << FORMAT16(state.BC) << " DE=" << FORMAT16(state.DE) << " HL=" << FORMAT16(state.HL) << " SP=" << FORMAT16(state.SP) << std::endl
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<< " PC=" << FORMAT16(state.PC)
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<< " HALT=" << state.halted << " HALTBUG=" << state.haltbug << " STOP=" << state.stopped;
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const std::string str = s.str();
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char* buf = new char[str.length()];
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std::strcpy(buf, str.c_str());
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return buf;
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}
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