VHDL Snippets

This commit is contained in:
madmaurice 2015-11-02 22:11:35 +01:00
parent 41f38f343b
commit 19c7c55d84

View file

@ -0,0 +1,35 @@
snippet entity
entity ${1} is
${2}
end entity ${1};
snippet architecture
architecture ${1}_impl of ${1} is
${2}
begin
${3}
end architecture ${1};
snippet case
case ${1} is
${2}
end case;
snippet if
if ${1} then
${2}
end if;
snippet elif
else if ${1}
${2}
snippet else
else
${1}
snippet lib
library ${1};
snippet use
use ${1}.all;