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a8edf40b96
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cpu/decoder - Unify code for ALU n ops
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2023-08-30 13:41:15 +02:00 |
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9bc6f935ac
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cpu/decoder - Fix comment
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2023-08-30 13:40:50 +02:00 |
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77bd32114a
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cpu/decoder - Join code for INC rr and DEC rr
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2023-08-30 13:34:14 +02:00 |
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e45704e2ab
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cpu/decoder - Reduct empty lines
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2023-08-30 13:27:04 +02:00 |
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dbd42c4573
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cpu/decoder - Remove extraneous brackets
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2023-08-30 13:26:35 +02:00 |
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87b939c80e
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cpu/decoder - add function with shared code for 16-bit addition
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2023-08-30 13:20:57 +02:00 |
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3d244d1ec0
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cpu/decoder - Implement DAA
This is a best effort implementation, possible quirks of the actual
hardware have not been considered.
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2023-08-30 12:56:00 +02:00 |
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2d4daf821e
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cpu/decoder - Add missing breaks
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2023-08-30 12:32:38 +02:00 |
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7d1d20becf
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cpu/decoder - Fix comment
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2023-08-30 00:36:20 +02:00 |
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efc6762068
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cpu/decoder - Remove extaneous code of instruction already implemented elsewhere
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2023-08-30 00:25:49 +02:00 |
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aec3c7b0e6
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cpu - Fix build errors
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2023-08-30 00:01:45 +02:00 |
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c4a9a10e09
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cpu/decoder - Treat undefined opcodes as NOP
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2023-08-29 23:59:32 +02:00 |
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c90788d330
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cpu/decoder - Implement STOP n8
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2023-08-29 23:47:18 +02:00 |
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4e506a4d3c
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cpu/decoder - Implement LD HL, SP + e8
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2023-08-29 23:46:09 +02:00 |
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7180ae8c40
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cpu/decoder - Implement HALT
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2023-08-29 23:32:11 +02:00 |
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eb0e591b25
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Move panic.h to misc
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2023-08-29 23:15:00 +02:00 |
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ef2615c1a7
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cpu/decoder - Fix build errors
|
2023-08-29 23:13:23 +02:00 |
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517577d546
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Improve consistency for including
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2023-08-29 23:11:31 +02:00 |
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c39a680293
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cpu/decoder - Fix IME state for RETI
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2023-08-29 23:06:50 +02:00 |
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28bc389644
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cpu/decoder - Reset carry flag for PREFIX SWAP instruction
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2023-08-29 23:06:28 +02:00 |
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b6f0f4416f
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cpu/decoder - Implement ADD SP, e8
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2023-08-29 23:06:05 +02:00 |
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41c4038d0a
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cpu/decoder - Implement ADD HL, rr
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2023-08-29 23:05:55 +02:00 |
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8f1b1eb924
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cpu/decoder - Implement INC rr and DEC rr
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2023-08-29 23:04:59 +02:00 |
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e893d2b9f5
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cpu/decoder - Use variable instead calculating twice
|
2023-08-29 23:04:31 +02:00 |
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43088a7f99
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cpu/decoder - Remove extraneous comments
|
2023-08-29 21:27:32 +02:00 |
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39e041f473
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cpu/decoder - Implement RLCA, RLA, RRCA, RRA
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2023-08-29 21:25:19 +02:00 |
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7902ac4641
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cpu/decoder - little code improvement
|
2023-08-29 21:14:19 +02:00 |
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50cac936b9
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cpu/decoder - Implement PREFIX (bit shift & bit ops)
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2023-08-29 21:00:37 +02:00 |
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8160037ffc
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cpu/decoder - Improve code formatting
|
2023-08-29 19:43:19 +02:00 |
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40b5d1d370
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cpu/decoder - Fix decoding of JR e instruction
|
2023-08-29 19:42:42 +02:00 |
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ddea64ec63
|
cpu/decoder - Remove unnessary intermediate variable
|
2023-08-29 16:54:17 +02:00 |
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c08fd5d68d
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cpu/decoder - Actually use pushStack16 and popStack16 for POP and PUSH
|
2023-08-29 16:53:53 +02:00 |
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310fb99ad2
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cpu/decoder - Simplify decoding by referencing registers by index
|
2023-08-29 16:53:20 +02:00 |
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763fe13f5a
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decoder - Disable debug printf
|
2023-08-28 23:08:33 +02:00 |
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bd2b577c6c
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decoder - Add parenthesis to bitwise ANDs
== has priority over & so a & b == c is parsed as a & (b == c)
|
2023-08-28 22:31:52 +02:00 |
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505478b840
|
Improve Cpu class and implement interrupts
|
2023-08-28 21:56:33 +02:00 |
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e4a6b1f9b4
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decoder - Simplify RST command
We can calculate the rst address directly from the op code.
|
2023-08-28 19:39:18 +02:00 |
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ad2334a6af
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Implement more parts of decoder
|
2023-08-27 22:19:02 +02:00 |
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93521e559c
|
Simplify decoder code somewhat.
|
2023-08-27 00:15:12 +02:00 |
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ab09bbd9b7
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more decoder code
|
2023-08-26 23:51:51 +02:00 |
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8d063c08ca
|
Fix build errors.
|
2023-08-26 21:17:47 +02:00 |
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ba5b55a196
|
WIP initial state
|
2023-08-26 19:04:02 +02:00 |
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